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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 adg725/ADG731 16-/32-channel, serially controlled 4 1.8 v to 5.5 v, 2.5 v, analog multiplexers spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. features 3-wire spi compatible serial interface 1.8 v to 5.5 v single supply 2.5 v dual-supply operation 4 on resistance 0.5 on resistance flatness 7 mm x 7 mm 48-lead chip scale package (csp) or 48-lead tqfp package rail-to-rail operation power-on reset 42 ns switching times single 32-to-1 channel multiplexer dual/differential 16-to-1 channel multiplexer ttl/cmos compatible inputs for functionally equivalent devices with parallel interface, see adg726/adg732 applications optical applications data acquisition systems communication systems relay replacement audio and video switching battery-powered systems medical instrumentation automatic test equipment functional block diagram s1 s32 sclk din sync d ADG731 input shift register s1a da s16a s1b s16b db adg725 input shift register sclk din sync general description the ADG731/adg725 are monolithic, cmos, 32-channel/ dual 16-channel analog multiplexers with a serially controlled 3-wire interface. the ADG731 switches one of 32 inputs (s1s32) to a common output, d. the adg725 can be config- ured as a dual mux switching one of 16 inputs to one output, or a differential mux switching one of 16 inputs to a differential output. these mulitplexers utilize a 3-wire serial interface that is com- patible with spi , qspi , microwire , and some dsp inter face standards. on power-up, the internal shift register contains all zeros and all switches are in the off state. these multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives high switch- ing speed with very low on resistance and leakage currents. they operate from a single supply of 1.8 v to 5.5 v or a 2.5 v dual supply, making them ideally suited to a variety of applications. on resistance is in the region of a few ohms, is closely matched between switches, and is very flat over the full signal range. these parts can operate equally well as either multiplexers or demultiplexers and have an input signal range that extends to the supplies. in the off condition, signal levels up to the sup- plies are blocked. all channels exhibit break-before-make switching action, preventing momentary shorting when switch- ing channels. the ADG731 and adg725 are serially controlled 32-channel, and dual/differential 16-channel multiplexers, respectively. they are available in either a 48-lead csp or tqfp package. product highlights 1. 3-wire serial interface 2. 1.8 v to 5.5 v single-supply or 2.5 v dual-supply operation. these parts are specified and guaranteed with 5 v 10%, 3 v 10% single-supply, and 2.5 v 10% dual-supply rails. 3. on resistance of 4 ? 4. guaranteed break-before-make switching action 5. 7 mm 7 mm 48-lead chip scale package (csp) or 48-lead tqfp package
rev. 0 ? adg725/ADG731?pecifications 1 (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter +25 o c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )4 ? typ v s = 0 v to v dd , i ds = 10 ma; 5.5 6 ? max test circuit 1 on resistance match between 0.3 ? typ v s = 0 v to v dd , i ds = 10 ma channels ( ? r on ) 0.8 ? max on resistance flatness (r flat(on) ) 0.5 ? typ v s = 0 v to v dd , i ds = 10 ma 1 ? max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.25 1n a max test circuit 2 drain off leakage i d (off) 0.05 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; adg725 0.5 2.5 na max test circuit 3 ADG731 1 5na max channel on leakage i d , i s ( on) 0.05 na typ v d = v s = 1 v or 4.5 v; adg725 0.5 2.5 na max test circuit 4 ADG731 1 5na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 42 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 53 62 ns max v s1 = 3 v/0 v, v s32 = 0 v/3 v break-before-make time delay, t d 30 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 3 v; test circuit 6 charge injection 5 pc typ v s = 2.5 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth adg725 34 mhz typ r l = 50 ? , c l = 5 pf; test circuit 10 ADG731 18 mhz typ c s (off) 15 pf typ f = 1 mhz c d (off) adg725 170 pf typ f = 1 mhz ADG731 340 pf typ f = 1 mhz c d , c s (on) adg725 175 pf typ f = 1 mhz ADG731 350 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v 20 a max notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
rev. 0 adg725/ADG731 ? specifications 1 (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter +25 o c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )7 ? typ v s = 0 v to v dd , i ds = 10 ma; 11 12 ? max test circuit 1 on resistance match between 0.35 ? typ v s = 0 v to v dd , i ds = 10 ma channels ( ? r on )1 ? max on resistance flatness (r flat(on) )3 ? max v s = 0 v to v dd , i ds = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.25 1n a max test circuit 2 drain off leakage i d (off) 0.05 na typ v s = 1 v/3 v, v d = 3 v/1 v; adg725 0.5 2.5 na max test circuit 3 ADG731 1 5na max channel on leakage i d , i s ( on) 0.05 na typ v s = v d = 1 v or 3 v; adg725 0.5 2.5 na max test circuit 4 ADG731 1 5na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 60 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 80 90 ns max v s1 = 2 v/0 v, v s32 = 0 v/2 v break-before-make time delay, t d 30 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 2 v; test circuit 6 charge injection 1 pc typ v s = 0 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth adg725 34 mhz typ r l = 50 ? , c l = 5 pf; test circuit 10 ADG731 18 mhz typ c s (off) 15 pf typ f = 1 mhz c d (off) adg725 170 pf typ f = 1 mhz ADG731 340 pf typ f = 1 mhz c d , c s (on) adg725 175 pf typ f = 1 mhz ADG731 350 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 5 a typ digital inputs = 0 v or 3.3 v 10 a max notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
rev. 0 ? adg725/ADG731 dual-supply specifications 1 (v dd = +2.5 v 10%, v ss = ?.5 v 10%, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter +25 o c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on )4 ? typ v s = v ss to v dd , i ds = 10 ma; 5.5 6 ? max test circuit 1 on resistance match between 0.3 ? typ v s = v ss to v dd , i ds = 10 ma channels ( ? r on ) 0.8 ? max on resistance flatness (r flat(on) ) 0.5 ? typ v s = v ss to v dd , i ds = 10 ma 1 ? max leakage currents v dd = +2.75 v, v ss = ?.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/1.25 v, v d = ?.25 v/+2.25 v; 0.25 0.5 na max test circuit 2 drain off leakage i d (off) 0.05 na typ v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; adg725 0.5 2.5 na max test circuit 3 ADG731 1 5na max channel on leakage i d , i s ( on) 0.01 na typ v s = v d = +2.25 v/?.25 v; test circuit 4 adg725 0.5 2.5 na max ADG731 1 5na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 55 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 75 84 ns max v s1 = 1.5 v/0 v, v s32 = 0 v/1.5 v break-before-make time delay, t d 15 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 1.5 v; test circuit 6 charge injection 1 pc typ v s = 0 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth adg725 34 mhz typ r l = 50 ? , c l = 5 pf; test circuit 10 ADG731 18 mhz typ c s (off) 13 pf typ c d (off) adg725 130 pf typ f = 1 mhz ADG731 260 pf typ f = 1 mhz c d , c s (on) adg725 150 pf typ f = 1 mhz ADG731 300 pf typ f = 1 mhz power requirements v dd = 2.75 v i dd 10 a typ digital inputs = 0 v or 2.75 v 20 a max i ss 10 a typ v ss = ?.75 v 20 a max digital inputs = 0 v or 2.75 v notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
rev. 0 adg725/ADG731 ? timing characteristics 1,2 parameter limit at t min , t max unit conditions/comments f sclk 30 mhz max sclk cycle frequency t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 40 ns min minimum sync low time t 6 5 ns min data setup time t 7 4.5 ns min data hold time t 8 33 ns min minimum sync high time notes 1 see figure 1. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. specifications subject to change without notice. sclk sync din db7 db0 t 8 t 4 t 5 t 6 t 7 t 2 t 3 t 1 figure 1. 3-wire serial interface timing diagram a3 a2 a1 a0 en csa x db0 (lsb) db7 (msb) data bits csb figure 2. adg725 input shift register contents a3 a2 a1 a0 en cs x db0 (lsb) db7 (msb) data bits a4 figure 3. ADG731 input shift register contents
rev. 0 ? adg725/ADG731 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg725/ADG731 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . .?.3 v to +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 v to ? v analog inputs 2 . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 2 . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c thermal impedance (four-layer board) 48-lead csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c/w 48-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6 c/w lead temperature, soldering (10 seconds) . . . . . . . . . . 300 c ir reflow, peak temperature (<20 seconds) . . . . . . . . 235 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at sclk, sync , din, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. ordering guide model temperature range package description package option adg725bcp ?0 o c to +85 o cc hip-scale package (csp) cp-48 adg725bsu ?0 o c to +85 o ct hin quad flatpack su-48 ADG731bcp ?0 o c to +85 o cc hip-scale package (csp) cp-48 ADG731bsu ?0 o c to +85 o ct hin quad flatpack su-48
rev. 0 adg725/ADG731 ? 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) s12b s11b s10b s9b s8b s7b s6b s12a s11a s10a s9a s8a s7a s6a nc = no connect s5a s4a s3a s2a s5b s4b s3b s2b adg725 s1a s1b s13a s14a s15a s16a nc da nc db s16a s15b s14b s13b v dd v dd nc nc sync din sclk nc nc nc gnd v ss 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) s28 s27 s26 s25 s24 s23 s22 s12 s11 s10 s9 s8 s7 s6 nc = no connect s5 s4 s3 s2 s21 s20 s19 s18 ADG731 s1 s17 s13 s14 s15 s16 nc d nc nc s32 s31 s30 s29 v dd v dd nc nc sync din sclk nc nc nc gnd v ss pin configurations pin function descriptions adg725 ADG731 mnemonic function 1-12, 25-40, 1-12, 25-40, sxx source. may be an input or output. 45-48 45-48 13, 14 13, 14 v dd power supply input. these parts can be operated from a single supply of 1.8 v to 5.5 v and a dual supply of 2.5 v. 17 17 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. an 8-bit counter is also enabled. data is transferred on the falling edges of the following clocks. after eight falling clock edges, switch conditions are automaticaly updated. sync may be used to frame the signal or just pulled low for a short period of time to enable the counter and input buffers. 18 18 din serial data input. data is clocked into the 8-bit input register on the falling edge of the serial clock input. 19 19 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. these devices can accommodate serial input rates of up to 30 mhz. 23 23 gnd ground reference 24 24 v ss most negative power supply in a dual-supply application. in single-supply applications, connect to gnd. 41, 43 43 d, da, db drain. may be an input or output. 48-lead csp and tqfp
rev. 0 ? adg725/ADG731 table i. adg725 truth table a3 a2 a1 a0 en en en en en csa csa csa csa csa csb csb csb csb csb switch condition xx xxx 11 retains previous switch condition xx xx1 xx all switches off 0000 000 s1a ?da, s1b ?db 0001 000 s2a ?da, s2b ?db 0010 000 s3a ?da, s3b ?db 0011 000 s4a ?da, s4b ?db 0100 000 s5a ?da, s5b ?db 0101 000 s6a ?da, s6b ?db 0110 000 s7a ?da, s7b ?db 0111 000 s8a ?da, s8b ?db 1000 000 s9a ?da, s9b ?db 10 01 000 s10a ?da, s10b ?db 10 10 000 s11a ?da, s11b ?db 10 11 000 s12a ?da, s12b ?db 11 00 000 s13a ?da, s13b ?db 11 01 000 s14a ?da, s14b ?db 11 10 000 s15a ?da, s15b ?db 11 11 000 s16a ?da, s16b ?db x = don? care table ii. ADG731 truth table a4 a3 a2 a1 a0 en en en en en cs cs cs cs cs switch condition xx xx xx1 retains previous switch condition xx xxx 1x all switches off 0000 000 1 0000 100 2 0001 000 3 0001 100 4 0010 000 5 0010 100 6 0011 000 7 0011 100 8 0100 000 9 0100 100 10 0101 000 11 0101 100 12 0110 000 13 0110 100 14 0111 000 15 0111 100 16 1000 000 17 1000 100 18 1001 000 19 1001 100 20 1010 000 21 1010 100 22 1011 000 23 1011 100 24 1100 000 25 1100 100 26 1101 000 27 1101 100 28 1110 000 29 1110 100 30 1111 000 31 1111 100 32 x = don? care
rev. 0 adg725/ADG731 ? terminology v dd most positive power supply potential v ss most negative power supply in a dual-supply application. in single-supply applications, connect to gnd. i dd positive supply current i ss negative supply current gnd ground (0 v) reference s source terminal. may be an input or output. dd rain terminal. may be an input or output. v d (v s )a nalog voltage on terminals d, s r on ohmic resistance between d and s r on on resistance match between any two channels r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) source leakage current with the switch ?ff i d (off) drain leakage current with the switch ?ff i d , i s (on) channel leakage current with the switch ?n v inl maximum input voltage for logic ? v inh minimum input voltage for logic ? i inl (i inh ) input current of the digital input c s (off) ?ff?switch source capacitance. measured with reference to ground. c d (off) ?ff?switch drain capacitance. measured with reference to ground. c d ,c s (on) ?n?switch capacitance. measured with reference to ground. c in digital input capacitance t transition delay time measured between the 50% points of the eighth clock falling edge and 90% points of the output when switching from one address state to another. t d ?ff?time measured between the 80% points of both switches when switching from one address state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an ?ff?switch. crosstalk a measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance. on response the frequency response of the ?n?switch insertion loss the loss due to the on resistance of the switch
rev. 0 ?0 adg725/ADG731?ypical performance characteristics v d , v s ?v 8 0.0 5.5 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1 2 3 4 5 6 7 v dd = 2.7v v dd = 3.0v v dd = 4.5v resistance ? v dd = 3.3v v dd = 5v v dd = 5.5v t a = 25 c v ss = 0v tpc 1. on resistance vs. v d (v s ), single supply v d , v s ?v 8 0.0 0 1 2 3 4 5 6 7 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 +85 c ?0 c resistance ? +25 c v ss = 0v tpc 4. on resistance vs. v d (v s ), single supply v d , v s ?v q inj ?pc 25 ?5 ? ? 5 ? 01234 20 5 0 ? ?0 15 10 t a = 25 c v dd = +2.5 v ss = ?.5 v dd = +3v v ss = 0v v dd = +5v v ss = 0v tpc 7. ADG731 charge injection vs. source voltage v d , v s ?v 8 ?.75 0 1 2 3 4 5 6 7 ?.75 ?.75 0.25 1.25 2.25 v dd = +2.25v v ss = ?.25v t a = 25 c v dd = +2.5v v ss = ?.5v v dd = +2.75v v ss = ?.75v resistance ? tpc 2. on resistance vs. v d (v s ), dual supply v d , v s ?v 8 ?.5 0 1 2 3 4 5 6 7 ?.0 ?.5 ?.0 ?.5 0.0 0.5 1.0 1.5 2.0 2.5 +85 c ?0 c +25 c resistance ? tpc 5. on resistance vs. v d (v s ), dual supply temperature ? c ?0 ?0 80 0204 060 time ?ns 80 70 0 30 20 10 60 40 50 v ss = 0v v dd = 3v v dd = 5v tpc 8. switching times vs. temperature v d , v s ?v 8 0.0 0 1 2 3 4 5 6 7 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 +85 c ?0 c v ss = 0v resistance ? +25 c tpc 3. on resistance vs. v d (v s ) for different temperatures, single supply temperature ? c 0.5 5 ?.5 15 85 25 35 45 55 65 75 0.4 0.3 0.2 0.1 0.0 ?.1 ?.2 ?.3 ?.4 v dd = 5v v ss = 0v current na i d (off) i d (on) i s (off) tpc 6. leakage currents vs. temperature v dd ?v 01 6 2345 logic threshold voltage ?v 1.8 1.6 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 t a = 25 c fa l l ing rising tpc 9. logic threshold voltage vs. supply voltage
rev. 0 adg725/ADG731 ?1 frequency ?mhz 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.03 0.1 1 10 100 ?0 ?0 v dd = 5v t a = 25 c a ttenuation ?db tpc 10. off isolation vs. frequency frequency ?mhz a ttenuation ?db 0.003 0.1 100 110 0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 v dd = 3v, 5v t a = 25 c tpc 11. crosstalk vs. frequency frequency ?mhz 0 ?4 ?2 ?0 ? ? ? ? 0.03 0.1 1 10 100 v dd = 5v t a = 25 c ADG731 adg725 a ttenuation ?db tpc 12. on response vs. frequency t est circuits r on = v 1 /i ds v s v1 i ds d s test circuit 1. on resistance s1 d v s gnd a v s s2 s32 en logic ? v dd v ss v dd v ss i s (off) v d test circuit 2. i s off v d s1 s2 s32 v s i d (off) d gnd v dd v dd a v ss v ss a test circuit 3. i d (off) i d ( on ) v d s1 s32 v s d a gnd v dd v dd v ss v ss a test circuit 4. i d (on)
rev. 0 ?2 adg725/ADG731 50% v out t transition 90% 90% t transition sclk 50% v out d v s1 * similar connection for adg725 gnd ADG731 * s1 s32 s2 to s31 v s32 r l 300 c l 35pf v dd v dd v ss v ss vs1 vs32 8th fa lling edge 8th fa lling edge test circuit 5. switching time of multiplexer, t transition v dd v dd v out d v s ADG731 * s 1 s3 2 r l 30 0 c l 35pf t ope n 80% 80% 0v v s sclk * similar connection for adg725 v ss v ss gnd v out s2 thru s31 8th falling edge test circuit 6. break-before-make delay, t open v out v out sclk q inj = c l v out v out d ADG731 * c l 1nf s r s v s v dd v dd * similar connection for adg725 gnd v ss v ss 8th falling edge test circuit 7. charge injection test circuits (continued)
rev. 0 adg725/ADG731 ?3 ADG731 * * similar connection for adg725 v s v out network analyzer r l gnd s d 50 off isolation = 20 log v out v s v dd 0.1 f v dd v ss 0.1 f v ss 50 50 test circuit 8. off isolation v dd d s2 s32 v s v out network analyzer r l s1 ADG731 * v dd v ss v ss gnd * similar connection for adg725 channel-to-channel crosstalk = 20log 10 50 50 50 v s v out ( ) test circuit 9. channel-to-channel crosstalk ADG731 * * similar connection for adg725 v s v out network analyzer r l gnd s d v dd 0.1 f v dd v ss 0.1 f v ss insertion loss = 20 log v out with switch v out without switch 50 50 test circuit 10. bandwidth power-on reset on power-up of the device, all switches will be in the off condition. the internal shift register is filled with zeros and will remain so until a valid write takes place. serial interface the adg725 and ADG731 have a 3-wire serial interface ( sync , sclk, and din) that is c ompatible with spi, qspi, and microwire interface standards and most dsps. figure 1 shows the timing diagram of a typical write sequence. data is written to the 8-bit shift register via din under the control of the sync and sclk signals. when sync goes low, the input shift register is enabled. an 8-bit counter is also enabled. data from din is clocked into the shift register on the falling edge of sclk. figures 2 and 3 show the contents of the input shift registers for these devices. when the part has received eight clock cycles after sync has been pulled low, the switches are automatically updated with the new configuration and the input shift register is disabled. the adg725 csa and csb data bits allow the user the flex- ibility to change the configuration of either or both banks of the multiplexer. microprocessor interfacing microprocessor interfacing to the adg725/ADG731 is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire inter face consisting of a clock signal, a data signal, and a synchronization signal. the adg725/ADG731 requires an 8-bit data-word with data valid on the falling edge of sclk. figures 4? illustrate simple 3-wire interfaces with popular microcontrollers and dsps. adsp-21xx to adg725/ADG731 interface the adsp-21xx family of dsps are easily interfaced to the adg725/ADG731 without the need for extra logic. figure 4 shows an example of an spi interface between the adg725/ ADG731 and the adsp-2191m. sck of the adsp-2191m drives the sclk of the mux, while the mosi output drives the serial data line, din. sync is driven from one of the port lines, in this case spixsel . adsp-2191m * mosi spi x sel sck * additional pins omitted for clarity adg725/ADG731 sync sclk din figure 4. adsp-2191m to adg725/ADG731 interface a serial interface between the adg725/ adg7 31and the adsp- 2191m sport is shown in figure 5. in this interface example,
rev. 0 ?4 adg725/ADG731 sport0 is used to transfer data to the switch. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsp? serial clock and clocked into the adg725/ADG731 on the falling edge of its sclk. the update of each switch condition takes place automatically after the eighth sclk falling edge, regardless of the frame sync condition. communication between two devices at a given clock speed is possible when the following specs are compatible: frame sync delay and frame sync setup and hold, data delay and data setup and hold, and sclk width. the adg725/adg31 expects a t 4 ( sync falling edge to sclk falling edge set-up time) of 13 ns minimum. consult the adsp-21xx user manual for information on clock and frame sync frequencies for the sport register. the sport control register should be set up as follows: tfsw = 1, alternate framing invtfs = 1, active low frame signal dtype = 00, right justify data isclk = 1, internal serial clock tfsr = 1, frame every word itfs = 1, internal framing signal slen = 0111, 8-bit data-word adsp-2191m * dt tfs sclk * additional pins omitted for clarity adg725/ADG731 sync sclk din figure 5. adsp-2191m to adg725/ADG731 interface 8051 to adg725/ADG731 interface a serial interface between the adg725/ADG731 and the 8051 is shown in figure 6. txd of the 8051 drives sclk of the adg725/ADG731, while rxd drives the serial data line, din. p3.3 is a bit-programmable pin on the serial port and is used to drive sync . the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the user will have to ensure that the data in the sbuf register is arranged correctly as the switch expects msb first. when data is to be transmitted to the switch, p3.3 is taken low. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between the adg725/ADG731 and micro- controller interface. 80c51/80l51 * rxd p3.3 txd * additional pins omitted for clarity adg725/ADG731 sync sclk din figure 6. 8051 to adg725/ADG731 interface mc68hc11 interface to adg725/ADG731 figure 7 shows an example of a serial interface between the adg725/ADG731 and the mc68hc11 microcontroller. sck of the 68hc11 drives the sclk of the mux, while the mosi output drives the serial data line, din. sync is driven from one of the port lines, in this case pc7. the 68hc11 is config- ured for master mode: mstr = 1, cpol = 0, and cpha = 1. when data is transferred to the part, pc7 is taken low, and data is transmitted msb first. data appearing on the mosi output is valid on the falling edge of sck. mc68hc11 * mosi pc7 sync sck * additional pins omitted for clarity adg725/ADG731 sclk din figure 7. mc68hc11 interface to adg725/ADG731 application circuits adg725/ADG731 in an optical network control loop the adg725/ADG731 can be used in optical network applica- tions that have higher port counts and greater multiplexing requirements. the adg725/ADG731 are well suited to these applications because they allow a single control circuit to con- nect a higher number of channels without increasing board size and design complexity. in the circuit shown in figure 8, the 0 v to 5 v outputs of the ad5532hs are amplified to a range of 0 v to 180 v and then used to control actuators that determine the position of mems mirrors in an optical switch. the exact position of each mirror is measured using sensors. the sensor readings are muxed using the ADG731, a 32-channel switch, and fed back to a single- channel 14-bit adc (ad7894). the control loop is driven by an adsp-2191l, a 32-bit dsp with an spi compatible sport interface. it writes data to the dac, controls the multiplexer, and reads data from the adc via a 3-wire serial interface. ......... 1 32 ad7894 adsp-2191m ......... 1 32 ADG731 ad5532hs mems m irror a rray sensors figure 8. optical network control loop expand the number of selectable serial devices using the adg725/ADG731 the sync p in of the adg725/ADG731 can be used to select one of a number of multiplexers. all devices receive the same serial clock and serial data, but only one device will receive the
rev. 0 adg725/ADG731 ?5 sync signal at any one time. the mux addressed will be deter- mined by the decoder. there will be some digital feedthrough from the digital input lines. using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. figure 9 shows a typical circuit. enable din sclk dgnd coded address decoder vdd en din sclk din sclk din sclk adg725/ ADG731 sync din sclk sync sync sync d d d d other spi device adg725/ ADG731 other spi device figure 9. addressing multiple adg725/ADG731s u sing a decoder
c02766??/02(0) printed in u.s.a. ?6 adg725/ADG731 outline dimensions 48-lead frame chip scale package [lfcsp] (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 4.70 2.25 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 5.50 ref seating plane 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vkkd-2 coplanarity 0.08 48-lead thin plastic quad flat package [tqfp] 7 mm 7 mm 1.00 mm body (su-48) dimensions shown in millemeters top view (pins down) 1 12 13 25 24 36 37 48 0.5 bsc 7.00 bsc sq 0.27 0.22 0.17 9.00 bsc sq seating plane 7 0 1.05 1.00 0.95 1.20 max 0.75 0.60 0.45 0.20 0.09 0 min 0.15 0.05 compliant to jedec standards ms-026-abc

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